1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method and, more particularly, to a technique adapted to eliminate drawbacks arising in association with a thinning in performing three-dimensional mounting intended for the high density design and multiple-pin design of semiconductor devices.
2. Description of the Related Art
Conventionally, various methods have been proposed as techniques for accomplishing the high density design and multiple-pin design of semiconductor devices. As one method, for example, there is an available method which involves fabricating a printed wiring board of multilayer structure by means of a build-up method and mounting elements such as semiconductor chips on the multilayer printed wiring board so as to obtain a device.
Also, as another method, there is an available method which involves, instead of fabricating a printed wiring board of multilayer structure, fabricating a printed wiring board by forming wiring patterns on both sides of one insulative substrate, fabricating a device by mounting elements such as semiconductor chips on the wiring patterns of one surface of the printed wiring board, and performing three-dimensional mounting by stacking such devices. According to this method, it is necessary to electrically interconnect the respective semiconductor chips mounted on each of the printed wiring boards. To this end, in each of the printed wiring boards are formed through holes which pierce the printed wiring board, and wiring patterns formed on both surfaces of the printed wiring board are electrically interconnected through plated films (conductor layers) formed on the inner surfaces of the through holes.
Also, as still another method of performing three-dimensional mounting, there is a conceivable method which involves: using a silicon (Si) substrate as a base material layer; forming a hole with a required depth in the silicon substrate; forming required device patterns (including circuit patterns, wiring patterns, or the like) after filling the hole with a conductor by plating, or the like, so that the device patterns are electrically connected to the conductor; covering the device patterns with insulating films formed of polyimide resin, or the like; exposing the conductor by polishing the back surface of the silicon substrate by means of a back-grinding method, or the like; fabricating a device by providing metal bumps (external connection terminals) on the exposed conductor; and stacking a required number of devices.
Likewise in this method, it is necessary to electrically interconnect each of the devices, and to this end, it is necessary to form through holes in the insulating film of the device, plate the inner surfaces of the through holes, and electrically connect device patterns via the plated film to metal bumps of an upper-positioned device.
As described above, various techniques have been proposed as techniques for accomplishing the high density design and multiple-pin design of semiconductor devices. Among these, in the technique utilizing a build-up method, the thickness of the printed wiring board is considerably increased because the printed wiring board is fabricated to have a multilayer structure. Accordingly, the scale of the whole semiconductor device in final form becomes large, resulting in a problem in that it is not possible to fully meet the recent requirement for thinning design.
Also, the method which involves forming a device by means of an insulative substrate and stacking a required number of devices, is favorable in terms of the high density design and multiple-pin design, compared with the above technique utilizing a build-up method, because a plurality of semiconductor chips are mutually three-dimensionally mounted. However, this method has a drawback in terms of the thinning design in the same manner as described above, because semiconductor chips are interposed between printed wiring boards.
On the other hand, the method which involves forming a device by means of a silicon substrate and stacking a required number of devices, is favorable in terms of the thinning design, because the thickness of the silicon substrate is reduced by polishing the back surface thereof. However, this method poses the following problems:
Namely, in this method, a mechanical polishing such as a back-grinding method is performed to make the silicon substrate thin, and accordingly, there is a limit to the thickness of the silicon substrate to be thinned due to mechanical shocks of the mechanical polishing. If the silicon substrate is made excessively thin, a problem would arise in that cracks occur in the silicon substrate and, in some cases, the silicon substrate may be broken or damaged.
Also, the surface on one side of the silicon substrate, on which device patterns are formed, is formed of an insulating film of polyimide resin, or the like, while the surface on another side is formed of a conductor. Namely, the two surfaces have different coefficients of thermal expansion, which causes a difference in stresses generated between the one surface and another surface. As a result, for example, when polishing treatment is performed, a problem arises in that the silicon substrate is warped.